1. Field of the Invention
This invention relates generally to computer memories, and more particularly to negatively charged unselected word lines for reducing subthreshold current in computer memories.
2. Description of the Related Art
Most integrated circuit devices are required to have some type of memory device for storing information. As a result, there is a growing trend to integrate embedded memory arrays directly onto the chip, such as an application specific integrated circuit (BASIC). Typically, when a memory device is embedded into a chip, the memory device (e.g., an SCRAM) is provided with data reading and writing circuitry defined by a plurality of transistors. However, transistor geometries currently are becoming smaller. That is, the transistor gate lengths are becoming thinner, hence the distance between a transistor's source and drain is shrinking. As a result, transistors are leaking current between the source and drain terminals when the transistors are OFF, that is, when VGS=0. Unfortunately, when transistors conduct current in this manner, memory devices experience degraded performance and can become non-functional.
FIG. 1 is a schematic diagram showing a section of a conventional memory array column 100. The conventional memory array column 100 includes a pair of bit lines 102a and 102b coupled to a plurality of wordlines 104a-104n. Each wordline 104a-104n addresses a core cell 101a-101n in the memory array column 100 defined by a first pass gate transistor 106, a second pass gate transistor 108, a first inverter 110, and a second inverter 112. In each core cell 101a-101n, the first pass gate transistor 106 includes a first terminal coupled to the bitline 102a and a second terminal coupled to both the input of the first inverter 110 and the output of the second inverter 112. In addition, the gate of the first pass gate transistor 106 is coupled to the wordline 104a-104n. The second pass gate transistor 108 includes a first terminal coupled to the complimentary bitline 102b and a second terminal coupled to both the input of the second inverter 112 and the output of the first inverter 110. As above, the gate of the second pass gate transistor 108 is coupled to the wordline 104a-104n. 
The value stored in each core cell 101a-101n depends on the voltage values stored on nodes 114 and 116, which are always the inverse of each other. Hence, when node 116 is high, node 114 is low, and vice versa. Generally, these node values are isolated from the bitlines 102a and 102b until the core cell 101a-101n is selected by driving the wordline 104a-104n to the core cell high. For example, during a read operation, the pass gate transistors 106 and 108 turn ON when the wordline 104a-104n is high, and allow the core cell to set the values of the bitlines.
Ideally, when reading core cell 101a, the bitlines 102a and 102b are first precharged to VDD. The wordline 104a is then asserted high to address the core cell 101a, turning ON pass gate transistors 106 and 108. If the core cell 101a stores a low at node 114 and a high at node 116, the voltage on bitline 102a is lowered via pass gate transistor 106, while the voltage on bitline 102b remains unchanged because the voltage on both terminals of pass gate transistor 108 is VDD. Hence, a voltage differential develops between the bitlines 102a and 102b, which can be sensed via a sense amp during the read operation.
Unfortunately, the small geometries of the pass gate transistors 106 and 108 result in a subthreshold leakage current flowing across the source and drain of the pass gate transistors 106 and 108. As a result, when a majority of core cells in a column store values different from the selected core cell, read problems can occur. For example, if core cell 101a stores a low on node 114 and a high on node 116, and the remaining core cells of the column store a high on node 114 and low on node 116, problems can occur when a read operation is performed on core cell 101a. 
In particular, during the read operation, wordline 104a is asserted high, turning on the pass gate transistors 106 and 108 of core cell 101a. Since node 114 of core cell 101a is low, a read current IR 120 flows from the bitline 102a across pass gate transistor 106, thus lowering the voltage on bitline 102a. However, as mentioned above, the small geometries of the pass gate transistors 106 and 108 result in a subthreshold leakage current. Hence, the pass gate transistor 108, which is coupled to the complementary bitline 102b, of each of the unselected core cells 101b-101n allows a subthreshold current ILeak 122 to flow from bitline 102b, thus slightly lowering the voltage on bitline 102b. 
On an individual core cell basis, this leakage current through the unslected pass transistors 108 in core cells 101b through 101n on the complementary bitline 102b is small, about 10 nA. However, generally a memory array includes in excess of one thousand core cells per column. As a result, the small subthreshold current is multiplied by one thousand, which results in a bitline current of several micro amps. Since both the read current IR 120 and the combined subthreshold leakage current ILeak 122 are several micro amps, the voltage on both the bitlines 102a and 102b drops at the same or approximately the same rate. Consequently, read performance and read errors occur.
FIG. 2A is a graph 200 showing conventional bitline voltages during a read operation wherein subthreshold read errors occur. As shown in graph 200, when the voltage on the wordline 104a rises, the voltage on both bitlines 102a and 102b falls at approximately the same rate. Hence, the voltage differential between the bitlines 102a and 102b is very small or zero. Consequently, the sense amp cannot sense the voltage differential between the bitlines 102a and 102b and as a result a read error occurs. The voltage levels of graph 200 generally result when the combined subthreshold leakage current of the unselected core cells approximates the read current of the selected core cell. However, read performance can also be affected when the combined subthreshold leakage current of the unselected core cells is less than the read current of the selected core cell, as described next with reference to FIG. 2B.
FIG. 2B is a graph 250 showing conventional bitline voltages during a read operation wherein subthreshold current degrades read performance. As shown in graph 250, when the voltage on the wordline 104a rises, the voltage on bitline 102a falls at a faster rate than the voltage on bitline 102b. Hence, the voltage differential 252 between the bitlines 102a and 102b eventually reaches a readable level. However, unlike an ideal read operation, wherein the voltage differential reaches a readable level at time t, the voltage differential 252 of FIG. 2B reaches a readable level at a later time t+Δt. Consequently, the time period required to sense the voltage differential between the bitlines 102a and 102b is increased and as a result performance is degraded.
To address this issue in DRAMs, charge pumps have conventionally been used to negatively charge the substrate, which increases the threshold voltage of transistors and reduces leakage. This is performed using triple well technology. Hence, the well of a core cell can be isolated and used to negatively charge the substrate, which effectively raises the threshold voltage of the transistors. Unfortunately, this slows the performance of the transistors in the DRAM. Moreover, SRAMs generally use CMOS technology, which does not include triple wells. Consequently, the substrate cannot be negatively charged in an SRAM without biasing all the transistors of the SRAM, which slows down all the logic of the SRAM.
In view of the foregoing, there is a need for a method that reduces subthreshold current in core cells. The method should reduce subthreshold current without reducing the performance of all the logic of the memory device, or the core cell. Moreover, the method should not require large area increases in the memory device.